1. Field of the Invention
This invention relates to a method for planarizing an integrated circuit structure. More particularly, this invention relates to a method for planarizing an integrated circuit structure using a low melting glass which is deposited over a layer of insulating material and then etched back. In a preferred embodiment, the etching step is carried out after the deposition step without an intervening exposure of the structure to ambient atmosphere, thus permitting the use of hygroscopic low melting glasses as planarizing material.
2. Description of the Related Art
In the formation of integrated circuit structures, patterning of layers to permit formation on a substrate of active devices such as transistors, passive devices such as resistors, and metal lines to interconnect devices, can result in the formation of uneven surfaces.
When a layer of insulating material such as silicon oxide is applied over such uneven surfaces, to permit the formation of further patterned layers thereover, the silicon oxide tends to conform to the underlying topography resulting in the creation of a nonplanar or stepped surface. It is very difficult to pattern further layers over such an uneven surface using standard lithography techniques.
It has, therefore, become the customary practice to apply planarizing layers of either photoresist or organic-based glass materials, such as "SOG" (Spin On Glass) which will etch at about the same rate as the underlying silicon oxide insulating layer. The structure is then anisotropically etched to remove the planarizing layer, as well as raised portions of the underlying silicon oxide layer.
However, both photoresist and SOG have what is called as a loading effect. This means that the etch rate of these materials depends upon how much of the insulating layer, e.g., the silicon oxide layer, is exposed. Thus, achieving an equal etch rate of both insulating material (silicon oxide) and the sacrificial or planarizing material is very difficult and the etch rate is, therefore, dependent upon the geometry of the structure. Furthermore, when the spaces between raised portions are less than about 1.5 microns, the spinning process of applying either of these two planarizing materials is not effective.
The above described planarizing materials also have limited step coverage and are also limited with respect to the total amount or thickness of these materials which can be deposited. Furthermore, since these planarizing materials are dispersed in organic binders and solvents, prior to application of such planarizing materials, the integrated circuit structure must be removed from a vacuum chamber in which the insulating layer such as silicon oxide is deposited, e.g., by CVD methods, in order to coat the structure with the planarizing layer. After such coating, the solvent in the planarizing coating must be allowed to evaporate and the planarizing coating must then be baked to remove further solvents and to harden the coating prior to the etching step, which is conventionally a dry etching process which is also usually carried out in a vacuum chamber.
Thus, the present planarizing processes not only yield unsatisfactory results, but also result in the need for a number of additional and time consuming intermediate steps outside of the vacuum apparatus which is normally used for the preceding CVD deposition of the underlying insulating layer as well as for the subsequent dry etching step which normally follows the formation of such a planarizing layer. Such additional steps not only add expense to the process, but also risk the possible introduction of undesirable contaminants to the surface of the integrated circuit structure by exposure of the integrated circuit structure to the atmosphere.
It would, therefore, be highly desirable to be able to planarize an integrated circuit structure without the use of such organic-based planarizing materials which require removal of the integrated circuit structure from the vacuum system for application, drying, and baking of a planarizing layer.